Blogs

Arindam Banerjee's picture

Mini plan and target set

I am working on mini plans for the project that would be given in Git repo as issues. The project will run as per solving the issues one by one. I will discuss with my mentor regarding this in more details. I need 1-2 day(s) to prepare a bunch of small targets (step by step).

1:1 with my mentor Rob

Unlike most participants, Rob and I are both at PSU. We met today to discuss the project timeline and repository. I know enough to start poking around in the code.

Arindam Banerjee's picture

Routability driven placement

As the main objective of PCB placement is to permit a high quality routing, a widely used parameter to define the placement quality is to minimize the total wirelength of all connections. However the exact wirelength of each net is not estimated until the nets are actually routed. Computation of the minimum wirelength of a single net is in general NP-hard, and it is represented graphically to compute the length of a minimum Steiner tree. I am currently studying on calculating wirelength parameter (generally estimated as Half Perimeter Wire Length - HPWL) methods to be minimized by the placer.

Studying on crawling Account Information by simulating browser && Sina API

First, building 4 components today: 1. User profile information retrieval component: by providing user's id or name, system could retrieve Weibo users' profile data as json format. 2. Retrieve latest users' posts component: get latest 20 weibo tweets every request. 3. Users' weibo tweets Collector: by simulating browser, program retrieve users' all weibo tweets simultaneously. One Weibo tweet include content,date,forward, pictures' url, emotions and so on. This part has not all finished yet, due to some other school work need to be done. 4. A sentiment analysis test GUI.

I will update more information tomorrow.

Arindam Banerjee's picture

Partitioning-Oriented Placement

Circuit partitioning plays an important role in PCB placement. I am studying on partitioning technique and related data structures to include in placement algorithm that will reduce components overlapping and also will make the implementation efficient.

Spinning up my development environment

Installed IE 10, a prerequisite for VS Express. Installed VS Express 2013 for Desktop. Installed LANDIS-II and recommended extensions (Age-only Succession, Base Fire, Base Wind, and Maximum Age Output). I was able to run a sample scenario using the command prompt. My task, this summer, is to replace this prompt with a GUI.

Arindam Banerjee's picture

Study and documentation

Mostly giving time in studying papers. Also today I created a github repo to start some documentation in wiki before coding period starts.

Arindam Banerjee's picture

PCB Placement - a heuristic approach

Most of the PCB placement algorithms used are heuristics that are based on the human knowledge about the problems. For larger problems, it is often useful to apply the recursive decomposition of circuit to reduce the problem size. I am still studying existing papers on PCB placement algorithms to shape my approach.

Reading up on C#

Reserved a couple of books today from the library to educate myself on C#. I am proficient in several languages but not the one I will use this summer. Had a difficult time tracking down books about the older versions of C#. My app needs to run on Windows XP as well as Windows 8 ...

Arindam Banerjee's picture

Thermal and electromagnetic effects in PCB placement

PCB components placement techniques are developed primarily on the basis of routability. But the placement has a great impact on thermal, electrical and mechanical characteristics of the circuit, size of component and production cost. As I am working on finalizing placement algorithm, the thermal effect and electromagnetic radiation noise should also be taken into account. I am doing some study on it to allow proper white space in placement to get rid of these problems in design.

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