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Could not work much yesterday except updating the existing partitioning code with ComponentToNet data structure. Will work on gain calculation now.
Now I am working on partitioning based placement with newly added data structure "ComponentToNet". Repetition of net Ids for a single component of this data structure needs to be removed otherwise gain calculation will not be done correctly. The PCB layout would have one vertical and two horizontal partitions for component placement.
Today I added a new data structure ComponentToNet that contains the component name and a list of net id connected to that component. I uploaded the code in git repo. It extracts data from netlist perser. I will use this in partitioning code.
I need to make some changes in partitioning code to get the exact gain as per algorithm. I am thinking of a new data structure 'componentToNet' that will hold the list of net Ids connected to a single component. I am working on it and if it works fine I will make the changes in my git repo.
Still working on the placement plan and studying related papers. Also made some small changes in partitioning code.
Till midterm, the basic partitioning was implemented. Now I will implement the placement algorithm. Today I studied the placement papers to make some proper plan before actual coding. I will also need to check how I can use existing data structure for placement. May be a little modification of algorithm would be needed before the implementation.
Midterm evaluation of GSoC-2014 is over and my project has passed the evaluation. Its time to make detailed plan for final submission. I will work on the main placement algorithm now. It will place the components optimally and the output file would be read by KiCAD tool.
Today it was the deadline for midterm submission. At this evaluation Google will decide whether to proceed further with the project or not. I could not work much today except testing modules with different circuits.
Now, as the basic component movement is working in FM algorithm, I am tweaking with partitioning code to find some improved result with less complexity. Also I am testing the partitioning code with circuits, designed by KiCAD, having different level of complexities to verify how overlapping of components are reduced.
Today I completed the project documentation part which has been developed till midterm evaluation phase. Instead of keeping seperate documents in repo, I have moved the documentation part in Github wiki pages. Also I am working on mapping the cell movement module for partitioning to placer code base in new branch.