Arindam Banerjee's blog

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Code scrubbing

I am trying to improve the documentation of this project. I have added the algorithmic details and areas for future enhancements. Also I am cleaning up the code by removing unnecessary comments and debugging information.

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Testing going on

As I am done with the placer, I am now doing more and more testing to find out any defect. I made a small change in measuring dimensions of components which are circular in shape.

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Debugging grid array

I found some small logical issues with grid array and corrected that. The placer is ready and I am now involved in testing. I will also add related documentation in github wiki page.

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Soft pencil down

Today it was the soft pencil down day and till date I have completed the PCB placer. The problem with grid array has been resolved. I will push the updates to git repo. I will make some small modifications in weekend. I plan to spend the next week for regression testing, documentation, debugging (if required) and code cleanup.

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Debugging final placement

The final placement algorithm has been included in main placer. I am facing one problem in layout grid formation. I found the reason and I am debugging this part. This algorithm will decide the final coordinates of the components on layout.

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Continuing Final placement

I am continuing with the final placement part. In each partition, components will be placed after checking overlapping. I have checked the algorithm seperately and now it will be included in main placer. The algorithm considers the layout as a grid and verifies grid location to place each component without overlapping.

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Final placement

I implemented HPWL calculation part. Now in final placement, I am working on overlapping removal in each partition. The components are stored in a data structure in decreasing order of size. Each component is picked up and checked if overlapping is there. Then overlapping is removed and component is placed on the layout. In each partition, placement starts from the corner of PCB's center. For block placement, perimeter is increased to keep white space for routing.

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HPWL

Placement quality is evaluated in terms of the half-perimeter wirelength (HPWL) of hyperedges in the original circuit hypergraph. I am working on writing a seperate method to calculate HPWL before and after placement. It will show how much minimization of wire length is possible after auto-placement. But I need to think if the net should be represented in clique model for measuring the HPWL.

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Placement

This placer employes partitioning approach for placing components on PCB layout. I am working on placement strategy in each partition where the final result would be written back to the PCB file. While changing the existing PCB file, I need to see which parameters need to be changed so that the final PCB file would be shown in KiCAD viewer with optimal placement.

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Still working on placement

I am still working on placing components in each partition. I need to work on placement angle of components and how their coordinates would be helpful to place them on PCB layout after partitioning.

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